Download Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog torrent

Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

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Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

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Description:

Communication Series P1 : Uart, Spi And I2C In Verilog

https://DevCourseWeb.com

Published 11/2023
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English | Size: 2.11 GB | Duration: 6h 51m

A Step-by-Step Guide

What you'll learn
Essential principles of UART, SPI, and I2C.
Implementation of UART 16550A, PMOD DA4.
Different Modes of SPI, Daisy Chain Configuration of SPI.
Bit Banging

Requirements
Fundamentals of Digital Electronics, Verilog.

Downloads:

Category:

Other /Tutorials

Size:

2.1 GB

Show Files »

[ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

Get Bonus Downloads Here.url (0.2 KB)

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1 - UART

1 - Simple UART TX.mp4 (80.1 MB)
10 - UART 16550 FIFO P4.mp4 (9.1 MB)
11 - FIFO TB.mp4 (30.1 MB)
12 - Design Code.html (5.5 KB)
13 - Testbench Code.html (0.8 KB)
14 - TUART 16550 TX Understanding Oversampling in Baud Generator.mp4 (47.8 MB)
15 - UART 16550 TX LCR Line Control Register.mp4 (90.0 MB)
16 - UART 16550 TX Stop bits.mp4 (46.9 MB)
17 - UART 16550 TX TX Logic.mp4 (49.7 MB)
18 - UART 16550 TX TX TB.mp4 (44.9 MB)
19 - Design Code.html (6.6 KB)
2 - Simple UART RX.mp4 (19.5 MB)
20 - TB Code.html (1.1 KB)
21 - UART 16550 RX RX Logic.mp4 (72.9 MB)
22 - UART 16550 RX RX TB.mp4 (45.7 MB)
23 - Design Code.html (8.3 KB)
24 - TB Code.html (1.1 KB)
25 - UART 16550 Registers Overview.mp4 (27.0 MB)
26 - UART 16550 Registers THR and RBR.mp4 (88.5 MB)
27 - UART 16550 Registers Divisor Latch.mp4 (40.1 MB)
28 - UART 16550 Registers FCR and LCR.mp4 (44.2 MB)
29 - UART 16550 Registers LSR.mp4 (45.7 MB)
3 - Simple UART TB.mp4 (41.0 MB)
30 - UART 16550 Registers TB.mp4 (37.1 MB)
31 - Design Code.html (13.1 KB)
32 - TB Code.html (1.2 KB)
33 - Complete Design.mp4 (12.2 MB)
34 - TX testbench.mp4 (62.8 MB)
35 - Design Code.html (33.8 KB)
36 - TB Code.html (1.0 KB)
4 - Design Code.html (3.6 KB)
5 - TB Code.html (0.9 KB)
6 - UART 16550A Overview.mp4 (16.1 MB)
7 - UART 16550 FIFO P1.mp4 (10.2 MB)
8 - UART 16550 FIFO P2.mp4 (40.7 MB)
9 - UART 16550 FIFO P3.mp4 (15.7 MB)

2 - SPI

37 - SPI protocol without different mode.mp4 (22.7 MB)
38 - SPI Master P1.mp4 (32.3 MB)
39 - SPI Master P2.mp4 (38.4 MB)
40 - SPI Master P3.mp4 (22.5 MB)
41 - Code.html (3.6 KB)
42 - SPI Slave P1.mp4 (10.2 MB)
43 - SPI Slave P2.mp4 (10.5 MB)
44 - Code.html (4.7 KB)
45 - Alternate Implementation.mp4 (23.6 MB)
46 - Code.html (3.2 KB)
47 - Understanding CPOL behavior.mp4 (75.9 MB)
48 - Implementation.mp4 (26.7 MB)
49 - Code.html (1.8 KB)
50 - Understanding CPHA.mp4 (35.6 MB)
51 - Understanding SPI Modes with different CPOL and CPHA.mp4 (16.8 MB)
52 - Working with CPHA Master.mp4 (27.3 MB)
53 - Master TB.mp4 (17.8 MB)
54 - Code.html (2.8 KB)
55 - Working with CPHA Slave.mp4 (21.4 MB)
56 - Code.html (3.2 KB)
57 - Digilent PMOD DA4 Analog Devices AD5628 Understanding Specifications.mp4 (63.5 MB)
58 - Digilent PMOD DA4 Analog Devices AD5628 Master Design.mp4 (23.5 MB)
59 - Digilent PMOD DA4 Analog Devices AD5628 TB.mp4 (14.9 MB)
60 - Design Code.html (3.2 KB)
61 - TB Code.html (0.4 KB)
62 - Daisy Chain Configuration.mp4 (18.3 MB)
63 - Master.mp4 (19.7 MB)
64 - Slave.mp4 (10.9 MB)
65 - Testbench.mp4 (31.4 MB)
66 - Design Code.html (5.4 KB)
67 - TB Code.html (0.3 KB)
68 - One Notes.html (0.8 KB)

3 - I2C

69 - Overview.mp4 (22.2 MB)
70 - Understanding I2C Open Drain Interface.mp4 (15.2 MB)
71 - Start and Stop Conditions.mp4 (16.8 MB)
72 - I2C Write and Read Transactions.mp4 (29.0 MB)
73 - I2C Master FSM without Clock Stretch.mp4 (12.9 MB)
74 - I2C Master without clock stretch.mp4 (184.7 MB)
75 - Master TB.mp4 (36.8 MB)
76 - Design Code.html (15.1 KB)
77 - TB Code.html (0.5 KB)
78 - I2C Slave without clock stretch.mp4 (87.6 MB)
79 - Testbench for top.mp4 (49.3 MB)
80 - Design Code.html (28.5 KB)
81 - TB Code.html (1.0 KB)
82 - Bit Banging.mp4 (56.3 MB)
83 - Understanding Clock Stretching.mp4 (20.1 MB)
84 - Implementation of Master.mp4 (16.4 MB)
85 - Implementation of Slave.mp4 (26.3 MB)
86 - Design Code.html (30.4 KB)
87 - TB Code.html (0.9 KB)

Bonus Resources.txt (0.4 KB)

files

Added:

2023-11-16 11:03:27

Language:

English

Peers:

Seeders : 2 , Leechers : 6

Tags:

IT & Software Hardware SystemVerilog Udemy

Release name:

Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

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Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog